module RegMemWb (
    input  [1:0]    MemtoReg,
    input           RegWrite,
    input  [31:0]   dm_data,
    input  [31:0]   alu_result,
    input  [4:0]    des_reg,
    input  [31:0]   pc,
    input           clk,
    output reg [1:0]   MemtoReg_out,
    output reg         RegWrite_out,
    output reg [31:0]  dm_data_out,
    output reg [31:0]  alu_result_out,
    output reg [4:0]   des_reg_out,
    output reg [31:0]  pc_out
);
    
    always @(posedge clk) begin
        pc_out <= pc;
        des_reg_out<=des_reg;
        MemtoReg_out<=MemtoReg;
        RegWrite_out<=RegWrite;
        dm_data_out<=dm_data;
        alu_result_out<=alu_result;
        
    end
endmodule //reg_mem_wb